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| ZL30108 SONET/SDH Network Interface DPLL Data Sheet Features * Supports output wander and jitter generation specifications for GR-253-CORE OC-3 and G.813 STM-1 SONET/SDH interfaces Accepts two input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs Provides a 19.44 MHz (SONET/SDH) clock output Provides an 8 kHz framing pulse and a 2 kHz multi-frame pulse Provides automatic entry into Holdover and return from Holdover Hitless reference switching Provides lock and accurate reference fail indication Loop filter bandwidth of 29 Hz or 14 Hz Less than 24 psrms intrinsic jitter on the 19.44 MHz output clock, compliant with GR-253-CORE OC-3 and G.813 STM-1 specifications Less than 0.5 nspp intrinsic jitter on output frame pulses External master clock source: clock oscillator or crystal Simple hardware control interface Ordering Information ZL30108LDA 32 pin QFN October 2004 * -40C to +85C Applications * Line card synchronization for SONET/SDH systems * * * * * * * Description The ZL30108 SONET/SDH network interface digital phase-locked loop (DPLL) provides timing and synchronization for SONET/SDH network interface cards. The ZL30108 generates a SONET/SDH clock and framing signals that are phase locked to one of two backplane or network references. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining tight phase alignment between the input reference clock and clock outputs. The ZL30108 output clock's wander and jitter generation are compliant with GR-253-CORE OC-3 and G.813 STM-1 specifications. * * * OSCi OSCo TIE_CLR LOCK Master Clock REF0 REF1 MUX TIE Corrector Circuit Virtual Reference DPLL Frequency Synthesizer C19o F8ko F2ko REF_FAIL0 REF_FAIL1 OOR_SEL REF_SEL RST MODE_SEL Reference Monitor TIE Corrector Enable Mode Control State Machine Frequency Select Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved. ZL30108 Table of Contents Data Sheet 1.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 Reference Select Multiplexer (MUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 Reference Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 Time Interval Error (TIE) Corrector Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Digital Phase Lock Loop (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.6 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.7 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.0 Control and Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Out of Range Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.1 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.2 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 Reference Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.0 Measures of Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 Jitter Generation (Intrinsic Jitter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4 Frequency Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.5 Holdover Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6 Capture Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 Lock Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8 Time Interval Error (TIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.9 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.10 Phase Continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.11 Phase Lock Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.0 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2 Zarlink Semiconductor Inc. ZL30108 List of Figures Data Sheet Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections (32 pin 5 mm X 5 mm QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3 - Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4 - Behavior of the Dis/Requalify Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 5 - Out-of-Range Thresholds for OOR_SEL=1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6 - Out-of-Range Thresholds for OOR_SEL=0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 7 - Timing Diagram of Hitless Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 8 - DPLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 9 - Mode Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10 - Recommended Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 11 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 12 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 13 - Power-Up Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 14 - Timing Parameter Measurement Voltage Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 15 - Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 16 - SONET/SDH Output Timing Referenced to F8ko . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3 Zarlink Semiconductor Inc. ZL30108 Data Sheet AVCORE 18 AGND 24 22 20 AGND AVDD C19o F2ko AVDD F8ko AGND REF_SEL REF0 REF1 OOR_SEL IC VDD TIE_CLR 32 2 30 28 26 ZL30108 16 GND AVDD 14 VDD IC 12 OSCi OSCo 33 IC (E-pad) 10 RST MODE_SEL 4 6 8 REF_FAIL0 REF_FAIL1 GND VCORE LOCK VCORE Figure 2 - Pin Connections (32 pin 5 mm X 5 mm QFN) 4 Zarlink Semiconductor Inc. AVCORE GND ZL30108 1.0 Pin # 1 2 3 4 Data Sheet Pin Description Name GND VCORE LOCK REF_FAIL0 Ground. 0 V Positive Supply Voltage. +1.8 VDC nominal Lock Indicator (Output). This output goes to a logic high when the PLL is frequency locked to the selected input reference. Reference 0 Failure Indicator (Output). A logic high at this pin indicates that the REF0 reference frequency has exceeded the out-of-range limit set by the OOR_SEL pin or that it is exhibiting abrupt phase or frequency changes. Reference 1 Failure Indicator (Output). A logic high at this pin indicates that the REF1 reference frequency has exceeded the out-of-range limit set by the OOR_SEL pin or that it is exhibiting abrupt phase or frequency changes. Positive Supply Voltage. +1.8 VDC nominal. Positive Analog Supply Voltage. +1.8 VDC nominal. Ground. 0 V Mode Select (Input). This input determines the mode of operation: See Table 3. 0: Normal mode (device locked to input reference) 1: Freerun mode Reset (Input). A logic low at this input resets the device. On power up, the RST pin must be held low for a minimum of 300 ns after the power supply pins have reached the minimum supply voltage. When the RST pin goes high, the device will transition into a Reset state for 3 ms. In the Reset state all outputs will be forced into high impedance. Oscillator Master Clock (Output). For crystal operation, a 20 MHz crystal is connected from this pin to OSCi. This output is not suitable for driving other devices. For clock oscillator operation, this pin must be left unconnected. Oscillator Master Clock (Input). For crystal operation, a 20 MHz crystal is connected from this pin to OSCo. For clock oscillator operation, this pin must be connected to a clock source. Internal Connection. Connect this pin to VDD. Positive Supply Voltage. +3.3 VDC nominal Positive Analog Supply Voltage. +3.3 VDC nominal Ground. 0 V Analog Ground. 0 V Positive Analog Supply Voltage. +1.8 VDC nominal Positive Analog Supply Voltage. +3.3 VDC nominal Multi Frame Pulse (Output). This is a CMOS 2 kHz active high 51 ns framing pulse, which marks the beginning of a multi frame. This clock output pad includes a Schmitt triggered input which serves as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels. Description 5 REF_FAIL1 6 7 8 9 VCORE AVCORE GND MODE_SEL 10 RST 11 OSCo 12 OSCi 13 14 15 16 17 18 19 20 IC VDD AVDD GND AGND AVCORE AVDD F2ko 5 Zarlink Semiconductor Inc. ZL30108 Pin # 21 Name C19o Description Data Sheet Clock 19.44 MHz (Output). This CMOS output is used in SONET/SDH applications. This clock output pad includes a Schmitt input which serves as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels. 22 23 24 AGND AVDD F8ko Analog Ground. 0 V Positive Analog Supply Voltage. +3.3 VDC nominal Frame Pulse (Output). This is an CMOS 8 kHz active high 31 ns framing pulse, which marks the beginning of a 125 us frame. This clock output pad includes a Schmitt input which serves as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels. 25 26 AGND REF_SEL Analog Ground. 0 V Reference Select 0 (Input/Output). As an input REF_SEL selects the reference input that is used for synchronization; See Table 4. 0: REF0 1: REF1 This pin is internally pulled down to GND. Reference (Input). This is one of two (REF0 and REF1) input reference sources used for synchronization. One of seven possible frequencies may be used: 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz,16.384 MHz or 19.44 MHz. This pin is internally pulled down to GND. Reference (Input). See REF0 pin description. Out Of Range Selection (Input). This input selects the frequency acceptance limits of the reference monitor: See Table 2. 0: 40 - 52 ppm 1: 64 - 83 ppm Internal Connection. Connect this pin to GND. Positive Supply Voltage. +3.3 VDC nominal. TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE) correction circuit resulting in a realignment of input phase with output phase. Internal Connection. Package E-pad, this pin is internally connected to device GND, it can be left unconnected or it can be connected to GND. 27 REF0 28 29 REF1 OOR_SEL 30 31 32 33 IC VDD TIE_CLR IC 6 Zarlink Semiconductor Inc. ZL30108 2.0 Functional Description Data Sheet The ZL30108 is a SONET/SDH Network Interface DPLL, providing timing (clock) and synchronization (frame) signals to SONET/SDH network interface cards. Figure 1 is a functional block diagram which is described in the following sections. 2.1 Reference Select Multiplexer (MUX) The ZL30108 accepts two simultaneous reference input signals and operates on their rising edges. One of two, the primary reference (REF0) or the secondary reference (REF1) signal is selected as input to the TIE Corrector Circuit based on the Reference Selection (REF_SEL) input. 2.2 Reference Monitor The input references are monitored by two independent reference monitor blocks, one for each reference. The block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is detected and the clock is continuously monitored for three independent criteria that indicate abnormal behavior of the reference signal, for example; long term drift from its nominal frequency or excessive jitter. To ensure proper operation of the reference monitor circuit, the minimum input pulse width restriction of 15 nsec must be observed. * Reference Frequency Detector (RFD): This detector determines whether the frequency of the reference clock is 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz 8.192 MHz, 16.384 MHz or 19.44 MHz and provides this information to the various monitor circuits and the phase detector circuit of the DPLL. Precise Frequency Monitor (PFM): This circuit determines whether the frequency of the reference clock is within the applicable accuracy range defined by the OOR_SEL pin, see Figure 5, Figure 6 and Table 2. It will take the precise frequency monitor up to 10 s to qualify or disqualify the input reference. Coarse Frequency Monitor (CFM): This circuit monitors the reference over intervals of approximately 30 s to quickly detect large frequency changes. Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large phase hits or the complete loss of the clock. * * * Reference Frequency Detector REF0 / REF1 OR REF_FAIL0 / REF_FAIL1 Precise Frequency Monitor Coarse Frequency Monitor dis/requalify timer Single Cycle Monitor OR REF_DIS Mode select state machine HOLDOVER REF_DIS= reference disrupted (internal signal) Figure 3 - Reference Monitor Circuit 7 Zarlink Semiconductor Inc. ZL30108 Data Sheet Exceeding the threshold of any of the monitors forces the corresponding REF_FAIL pin to go high. The single cycle and coarse frequency failure flags force the DPLL into Holdover mode and feed a timer that disqualifies the reference input signal when the failures are present for more than 2.5 s. The single cycle and coarse frequency failures must be absent for 10 s to let the timer requalify the input reference signal as valid. Multiple failures of less than 2.5 s each have an accumulative effect and will disqualify the reference. This is illustrated in Figure 4. SCM or CFM failure current REF timer 2.5 s REF_FAIL HOLDOVER 10 s Figure 4 - Behavior of the Dis/Requalify Timer When the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal mode with the output signal locked to the input signal. Each of the monitors has a built-in hysteresis to prevent flickering of the REF_FAIL status pin at the threshold boundaries. The precise frequency monitor and the timer do not affect the mode (Holdover/Normal) of the DPLL. C20i Clock Accuracy C20 0 ppm -83 -64 0 64 83 Out of Range In Range Out of Range In Range 96 115 C20 +32 ppm -51 -32 32 C20 -32 ppm -115 -96 -32 32 51 Out of Range In Range Frequency offset [ppm] -100 -75 -50 -25 0 25 50 75 100 Figure 5 - Out-of-Range Thresholds for OOR_SEL=1 8 Zarlink Semiconductor Inc. ZL30108 Data Sheet C20i Clock Accuracy C20 0 ppm -52 -40 0 40 52 Out of Range In Range C20 Out of Range In Range 60 72 +20 ppm -32 -20 20 C20 -20 ppm -72 -60 -32 20 32 Out of Range In Range Frequency offset [ppm] -100 -75 -50 -25 0 25 50 75 100 Figure 6 - Out-of-Range Thresholds for OOR_SEL=0 2.3 Time Interval Error (TIE) Corrector Circuit The TIE Corrector Circuit eliminates phase transients on the output clock that may occur in the course of recovery from Automatic Holdover mode to Normal mode. On recovery from Automatic Holdover mode or when switching to another reference input, the TIE corrector circuit measures the phase delay between the current phase (feedback signal) and the phase of the selected reference signal. This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL minimizes the phase transient it experiences when it switches to another reference input or recovers from Automatic Holdover mode. The delay value can be reset by setting the TIE Corrector Circuit Clear pin (TIE_CLR) low for at least 15 ns. This results in a phase alignment between the input reference signal and the output clocks and frame pulses as shown in Figure 15 and Figure 16. The speed of the phase alignment correction is limited by the loop filter bandwidth. Convergence is always in the direction of least phase travel. TIE_CLR can be kept low continuously. In that case the output clocks will always align with the selected input reference. This is illustrated in Figure 7. 9 Zarlink Semiconductor Inc. ZL30108 TIE_CLR = 0 locked to REF0 REF0 REF0 Data Sheet TIE_CLR = 1 locked to REF0 REF1 REF1 Output Clock Output Clock locked to REF1 REF0 REF0 locked to REF1 REF1 REF1 Output Clock Output Clock Figure 7 - Timing Diagram of Hitless Reference Switching 10 Zarlink Semiconductor Inc. ZL30108 2.4 Digital Phase Lock Loop (DPLL) Data Sheet The DPLL of the ZL30108 consists of a phase detector, a integrated on-chip loop filter and an digitally controlled oscillator as shown in Figure 8. The data path from the phase detector to the filter is tapped and routed to the lock indicator that provides a lock indication which is output at the LOCK pin. lock indicator virtual reference from TIE corrector circuit LOCK phase detector loop filter digitally controlled oscillator DPLL reference to frequency synthesizer state select from control state machine feedback signal from frequency select MUX Figure 8 - DPLL Block Diagram Phase Detector - the phase detector compares the virtual reference signal from the TIE corrector circuit with the feedback signal and provides an error signal corresponding to the phase difference between the two. This error signal is passed to the loop filter circuit. Loop Filter - the loop filter is similar to a first order low pass filter with bandwidth of 29 Hz, suitable to provide timing and synchronization for SONET/SDH network interface cards. Detected REF Frequency 2 kHz 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz Loop Filter Bandwidth 14 Hz 29 Hz Table 1 - Loop Filter Bandwidth Settings 11 Zarlink Semiconductor Inc. ZL30108 Data Sheet Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on the state of the ZL30108. In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input reference signal. In the Automatic Holdover mode, the DCO is free running at a frequency equal to the frequency that the DCO was generating in Normal Mode. The frequency in the Automatic Holdover mode is calculated from frequency samples stored 26 ms to 52 ms before the ZL30108 entered the Automatic Holdover mode. This ensures that the coarse frequency monitor and the single cycle monitor have time to disqualify a bad reference before it corrupts the holdover frequency. In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source. Lock Indicator - the lock detector monitors if the output value of the phase detector is within the phase-lockwindow for a certain time. The selected phase-lock-window guarantees the stable operation of the LOCK pin with maximum network jitter and wander on the reference input. If the DPLL goes into the Automatic Holdover mode, the LOCK pin will initially stay high for 0.1 s. If at that point the DPLL is still in the Automatic Holdover mode, the LOCK pin will go low. In Freerun mode the LOCK pin will go low immediately. 2.5 Frequency Synthesizers The output of the DCO is used by the frequency synthesizers to generate the output clocks and frame pulses which are synchronized to one of the input references (REF0 or REF1). The frequency synthesizer uses digital techniques to generate output clocks and advanced noise shaping techniques to minimize the output jitter. The clock and frame pulse outputs have limited drive capability and should be buffered when driving high capacitance loads. 2.6 State Machine As shown in Figure 1, the state machine controls the TIE Corrector Circuit and the DPLL. The control of the ZL30108 is based on the input MODE_SEL. 2.7 Master Clock The ZL30108 can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section. 12 Zarlink Semiconductor Inc. ZL30108 3.0 3.1 Data Sheet Control and Modes of Operation Out of Range Selection The frequency out of range limits for the precise frequency monitoring in the reference monitors are selected by the OOR_SEL pin, see Table 2. OOR_SEL 0 1 Out Of Range Limits 40 - 52 ppm 64 - 83 ppm Table 2 - Out of Range Limits Selection 3.2 Modes of Operation The ZL30108 has two possible manual modes of operation; Normal and Freerun. These modes are selected with mode select pins MODE_SEL as is shown in Table 3. Transitioning from one mode to the other is controlled externally. MODE_SEL 0 1 Mode Normal (with automatic Holdover) Freerun Table 3 - Operating Modes 3.2.1 Freerun Mode Freerun mode is typically used when an independent clock source is required, or immediately following system power-up before network synchronization is achieved. In Freerun mode, the ZL30108 provides timing and synchronization signals which are based on the master clock frequency (supplied to OSCi pin) only, and are not synchronized to the reference input signals. The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a 32 ppm output clock is required, the master clock must also be 32 ppm. See Applications - Section 5.2, "Master Clock". 3.2.2 Normal Mode Normal mode is typically used when a system clock source, synchronized to the network or a backplane is required. In Normal mode, the ZL30108 provides timing and frame synchronization signals, which are synchronized to one of two reference inputs (REF0 or REF1). The input reference signal may have a nominal frequency of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz. The frequency of the reference inputs are automatically detected by the reference monitors. When the Normal mode is selected through the MODE_SEL pin, the ZL30108 will automatically go into the Automatic Holdover mode if the currently selected reference is disrupted (see Figure 9). After the power up reset, the ZL30108 will initially go into the Automatic Holdover mode, generating clocks with the same accuracy as it would be in the Freerun mode. If the currently selected reference is not disrupted (see Figure 3), the state machine takes the DPLL out of the Automatic Holdover mode. The transition is done through the TIE correction state and the current phase offset of the output signals to the input reference is maintained. 13 Zarlink Semiconductor Inc. ZL30108 Data Sheet If the current reference experiences an disruption while the device is in Normal mode, the device will go automatically into Automatic Holdover mode. It will return to Normal mode as soon as the reference is valid again. If the reference selection changes because the value of the REF_SEL pin change the ZL30108 goes into Automatic Holdover mode and returns to Normal mode through the TIE correction state. Normal (locked) REF_DIS=0 and REF_CH=0 RST REF_DIS=0 REF_DIS=1 REF_DIS=1 REF_CH=1 Holdover (REF_DIS=0) or REF_CH=1 REF_DIS=1: Current selected reference disrupted (see Figure 3) REF_CH= 1: Reference change, a transition in the reference selection (a change in the REF_SEL pin). TIE Correction Figure 9 - Mode Switching in Normal Mode Automatic Holdover Mode Automatic Holdover mode is typically used for short durations while system synchronization is temporarily disrupted. In Automatic Holdover mode, the ZL30108 provides timing and synchronization signals, which are not locked to an external reference signal, but are based on storage techniques. The storage value is determined while the device is in Normal Mode and locked to an external reference signal. When in Normal Mode, and locked to the input reference signal, a numerical value corresponding to the ZL30108 output reference frequency is stored alternately in two memory locations every 26 ms. When the device is switched into Automatic Holdover mode, the value in memory from between 26 ms and 52 ms is used to set the output frequency of the device. The frequency accuracy of Automatic Holdover mode is 0.01 ppm. Two factors affect the accuracy of Automatic Holdover mode. One is drift on the master clock while in Automatic Holdover mode, drift on the master clock directly affects the Automatic Holdover mode accuracy. Note that the absolute master clock (OSCi) accuracy does not affect Holdover accuracy, only the change in OSCi accuracy while in Holdover. For example, a 32 ppm master clock may have a temperature coefficient of 0.1 ppm per C. So a 10 C change in temperature, while the ZL30108 is in the Automatic Holdover mode may result in an additional offset (over the 0.01 ppm) in frequency accuracy of 1 ppm, which is much greater than the 0.01 ppm of the ZL30108. The other factor affecting the accuracy is large jitter on the reference input prior (26 ms to 52 ms) to the mode switch. 14 Zarlink Semiconductor Inc. ZL30108 3.3 Reference Selection Data Sheet The active reference input (REF0 or REF1) is selected by the REF_SEL pin as shown in Table 4. If the logic value of the REF_SEL pin is changed when the DPLL is in Normal mode, the ZL30108 will perform a hitless reference switch. REF_SEL (input pin) 0 1 Input Reference Selected REF0 REF1 Table 4 - Manual Reference Selection When the REF_SEL inputs are used to force a change from the currently selected reference to another reference, the action of the LOCK output will depend on the relative frequency and phase offset of the old and new references. Where the new reference has enough frequency offset and/or TIE-corrected phase offset to force the output outside the phase-lock-window, the LOCK output will de-assert, the lock-qualify timer is reset, and LOCK will stay de-asserted for the full lock-time duration. Where the new reference is close enough in frequency and TIEcorrected phase for the output to stay within the phase-lock-window, the LOCK output will remain asserted through the reference-switch process. 4.0 Measures of Performance The following are some PLL performance indicators and their corresponding definitions. 4.1 Jitter Generation (Intrinsic Jitter) Timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. Wander is defined as the low-frequency variation of the clock edges from their ideal positions in time. High and low frequency variation imply phase oscillation frequencies relative to some demarcation frequency. (Often 10 Hz or 20 Hz for DS1 or E1, higher for SONET/SDH clocks.) Jitter parameters given in this data sheet are total timing jitter numbers, not cycle-to-cycle jitter. 4.2 Jitter Tolerance Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied jitter magnitude and jitter frequency depends on the applicable standards. 4.3 Jitter Transfer Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. For the ZL30108, the internal low pass loop filter determines the jitter attenuation. Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (for example 75% of the specified maximum tolerable input jitter). 4.4 Frequency Accuracy Frequency accuracy is defined as the absolute accuracy of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. For the ZL30108, the Freerun accuracy is equal to the master clock (OSCi) accuracy. 15 Zarlink Semiconductor Inc. ZL30108 4.5 Holdover Accuracy Data Sheet Holdover accuracy is defined as the absolute frequency accuracy of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. For the ZL30108, the storage value is determined while the device is in Normal Mode and locked to an external reference signal. 4.6 Capture Range Also referred to as pull-in range. This is the input frequency range over which the PLL must be able to pull into synchronization. The ZL30108 capture range is equal to 130 ppm minus the accuracy of the master clock (OSCi). For example, a +32 ppm master clock results in a capture range of +162 ppm on one side and -98 ppm on the other side of frequency range. 4.7 Lock Range This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock range is equal to the capture range for the ZL30108. 4.8 Time Interval Error (TIE) TIE is the time delay between a given timing signal and an ideal timing signal. 4.9 Maximum Time Interval Error (MTIE) MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period. 4.10 Phase Continuity Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency. Phase continuity applies to the output of the PLL after a signal disturbance due to a reference switch or a mode change. The observation period is usually the time from the disturbance, to just after the synchronizer has settled to a steady state. 4.11 Phase Lock Time This is the time it takes the PLL to phase lock to the input signal. Phase lock occurs when the input signal and output signal are aligned in phase with respect to each other within a certain phase distance (not including jitter). Lock time is affected by many factors which include: * * * * initial input to output phase difference initial input to output frequency difference PLL loop filter bandwidth in-lock phase distance The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and frequency. Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements. For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock time. See Section 6.2, "Performance Characteristics" for Maximum Phase Lock Time. 16 Zarlink Semiconductor Inc. ZL30108 5.0 Applications Data Sheet This section contains ZL30108 application specific details for power supply decoupling, clock and crystal operation, reset operation,and control operation. 5.1 Power Supply Decoupling It is recommended to place a 100 nF decoupling capacitor close to the power and ground pairs as shown in Figure 11 to ensure optimal jitter performance. 3.3 V 23 AV DD 100 nF 25 AGND 19 AV DD 100 nF 22 AGND 15 AV DD 100 nF 17 AGND 14 V DD 100 nF 16 GND 31 V DD 100 nF 1 GND V CORE 6 100 nF GND 8 V CORE 2 100 nF GND 1 AV CORE 18 100 nF AV CORE 7 100 nF 1.8 V ZL30108 Figure 10 - Recommended Power Supply Decoupling 17 Zarlink Semiconductor Inc. ZL30108 5.2 Master Clock Data Sheet The ZL30108 can use either a clock or crystal as the master timing source. Zarlink Application Note ZLAN-68 lists a number of applicable oscillators and crystals that can be used with the ZL30108. 5.2.1 Clock Oscillator When selecting a Clock Oscillator, numerous parameters must be considered. These includes absolute frequency, frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise. 1 2 3 4 Frequency Tolerance Rise & Fall Time Duty Cycle 20 MHz As required <10 ns 40% to 60% Table 5 - Typical Clock Oscillator Specification The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30108 and the OSCo output should be left open as shown in Figure 11. ZL30108 OSCi +3.3 V +3.3 V 20 MHz OUT GND 0.1 F OSCo No Connection Figure 11 - Clock Oscillator Circuit 18 Zarlink Semiconductor Inc. ZL30108 5.2.2 Crystal Oscillator Data Sheet Alternatively, a Crystal Oscillator may be used. A complete oscillator circuit made up of a crystal, resistor and capacitors is shown in Figure 12. The accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance. Typically, for a 20 MHz crystal specified with a 32 pF load capacitance, each 1 pF change in load capacitance contributes approximately 9 ppm to the frequency deviation. Consequently, capacitor tolerances and stray capacitances have a major effect on the accuracy of the oscillator frequency. The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses. The crystal specification is as follows. 1 2 3 4 5 6 Frequency Tolerance Oscillation Mode Resonance Mode Load Capacitance Maximum Series Resistance 20 MHz As required Fundamental Parallel As required 50 Table 6 - Typical Crystal Oscillator Specification ZL30108 OSCi 20 MHz 1 M OSCo 100 1 H The 100 resistor and the 1 H inductor may improve stability and are optional. Figure 12 - Crystal Oscillator Circuit 19 Zarlink Semiconductor Inc. ZL30108 5.3 Power Up Sequence Data Sheet The ZL30108 requires that the 3.3 V is not powered after the 1.8 V. This is to prevent the risk of latch-up due to the presence of parasitic diodes in the IO pads. Two options are given: 1. Power-up 3.3 V first, 1.8 V later 2. Power up 3.3 V and 1.8 V simultaneously ensuring that the 3.3 V power is never lower than 1.8 V minus a few hundred millivolts (e.g., by using a schottky diode or controlled slew rate) 5.4 Reset Circuit A simple power up reset circuit with about a 300 us reset low time is shown in Figure 13. Resistor RP is for protection only and limits current into the RST pin during power down conditions. The reset low time is not critical but should be greater than 300 ns. ZL30108 +3.3 V R 10 k RST RP 1 k C 10 nF Figure 13 - Power-Up Reset Circuit 20 Zarlink Semiconductor Inc. ZL30108 6.0 6.1 Data Sheet Characteristics AC and DC Electrical Characteristics Parameter Symbol VDD_R VCORE_R VPIN VOSC IPIN TST PPD VESD -55 Min. -0.5 -0.5 -0.5 -0.3 Max. 4.6 2.5 6 VDD + 0.3 30 125 195 2k Units V V V V mA C mW V Absolute Maximum Ratings* 1 2 3 4 5 6 7 8 Supply voltage Core supply voltage Voltage on any digital pin Voltage on OSCi and OSCo pin Current on any pin Storage temperature Package power dissipation ESD rating * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. * Voltages are with respect to ground (GND) unless otherwise stated Recommended Operating Conditions* Characteristics 1 2 3 Supply voltage Core supply voltage Operating temperature Sym. VDD VCORE TA Min. 2.97 1.62 -40 Typ. 3.30 1.80 25 Max. 3.63 1.98 85 Units V V C * Voltages are with respect to ground (GND) unless otherwise stated. DC Electrical Characteristics* Characteristics 1 2 3 4 5 Supply current with: OSCi = 0 V OSCi = Clock Core supply current with: OSCi = 0 V OSCi = Clock Schmitt trigger Low to High threshold point Schmitt trigger High to Low threshold point Input leakage current Sym. IDDS IDD ICORES ICORES VCIH 1.47 Min. 2.5 Max. 7.0 43 20 18 1.85 Units mA mA uA mA V All device inputs are Schmitt trigger type. Notes outputs loaded with 30 pf Outputs unloaded 6 7 VCIL IIL 0.8 -105 1.1 105 V A VI=VDD or 0 V 21 Zarlink Semiconductor Inc. ZL30108 DC Electrical Characteristics* Characteristics 8 High-level output voltage Sym. VOH Min. 2.4 Max. Units V Data Sheet Notes IOH = 8 mA for clock and framepulse outputs, 4 mA for status outputs IOL = 8 mA for clock and framepulse outputs, 4 mA for status outputs 9 Low-level output voltage VOL 0.4 V * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Voltages are with respect to ground (GND) unless otherwise stated. AC Electrical Characteristics* - Timing Parameter Measurement Voltage Levels (see Figure 14). Characteristics 1 2 Threshold Voltage Rise and Fall Threshold Voltage High Sym. VT VHM CMOS 1.5 2.0 0.8 Units V V V 3 Rise and Fall Threshold Voltage Low VLM * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Voltages are with respect to ground (GND) unless otherwise stated. Timing Reference Points ALL SIGNALS tIRF, tORF tIRF, tORF V HM VT V LM Figure 14 - Timing Parameter Measurement Voltage Levels. 22 Zarlink Semiconductor Inc. ZL30108 AC Electrical Characteristics* - Input timing for REF0 and REF1 references (see Figure 15). Characteristics 1 2 3 4 5 6 7 8 2 kHz reference period 8 kHz reference period 1.544 MHz reference period 2.048 MHz reference period 8.192 MHz reference period 16.384 MHz reference period 19.44 MHz reference period reference pulse width high or low Symbol tREF2kP tREF8kP tREF1.5P tREF2P tREF8P tREF16P tREF8kP tREFW Min. 483 120 338 263 63 38 38 15 Typ. 500 125 648 488 122 61 51 Data Sheet Max. 516 128 950 712 175 75 75 Units s s ns ns ns ns ns ns * Supply voltage and operating temperature are as per Recommended Operating Conditions. * Period Min/Max values are the limits to avoid a single-cycle fault detection. Short-term and long-term average periods must be within Out-ofRange limits. AC Electrical Characteristics* - Input to output timing for REF0 and REF1 references (see Figure 15). Characteristics 1 2 3 4 5 6 7 8 9 2 kHz reference input to F2ko delay 2 kHz reference input to F8ko delay 8 kHz reference input to F8ko delay 1.544 MHz reference input to F8ko delay 2.048 MHz reference input to F8ko delay 8.192 MHz reference input to F8ko delay 16.384 MHz reference input to F8ko delay 19.44 MHz reference input to C19o delay 19.44 MHz reference input to F8ko delay Symbol tREF2kD tREF2k_F8kD tREF8kD tREF1.5_F8kD tREF2_F8kD tREF8_F8kD tREF16_F8kD tREF19D tREF19_F8kD Min. 0 -27.2 -0.3 -1.1 -1.1 -0.6 29.0 0.2 -1.7 Max. 1.2 -26.5 2 0.9 0.9 0.8 30.6 1.1 1 Units ns ns ns ns ns ns ns ns ns * Supply voltage and operating temperature are as per Recommended Operating Conditions. 23 Zarlink Semiconductor Inc. ZL30108 tREF Data Sheet REF0/1 output clock with the same frequency as REF tREF tREF8D, tREF F8ko Figure 15 - Input to Output Timing AC Electrical Characteristics* - Output Timing (see Figure 16). Characteristics 1 2 3 4 5 7 C19o delay C19o pulse width low F2ko delay F2ko pulse width high F8ko pulse width high Output clock and frame pulse rise or fall time (with 30 pF load) Sym. tC19D tC19L tF2kD tF2kH tF8kH tORF Min. -1.0 25.0 25.0 51.1 30.0 1.1 Max. 0.5 25.8 26.6 52 31.8 2.3 Units ns ns ns ns ns ns * Supply voltage and operating temperature are as per Recommended Operating Conditions. tF8kH F8ko tC19L tC19D C19o tF2D tF2kH F2ko Figure 16 - SONET/SDH Output Timing Referenced to F8ko 24 Zarlink Semiconductor Inc. ZL30108 AC Electrical Characteristics* - OSCi 20 MHz Master Clock Input Characteristics 1 2 4 5 6 Duty cycle Rise time Fall time Oscillator Tolerance Sym. Min. -20 -32 40 Typ. Max. +20 +32 60 10 10 Units ppm ppm % ns ns Data Sheet Notes OOR_SEL=0 OOR_SEL=1 * Supply voltage and operating temperature are as per Recommended Operating Conditions. 6.2 Performance Characteristics Characteristics Min. Typ. 0.01 NA Max. Units ppm ppm Determined by stability of the 20 MHz Master Clock oscillator The 20 MHz Master Clock oscillator set at 0.ppm The 20 MHz Master Clock oscillator set at 0 ppm and OOR_SEL=1 The 20 MHz Master Clock oscillator set at 0 ppm and OOR_SEL=0 input reference = 2 kHz, 100 ppm frequency offset input reference 2 kHz, 100 ppm frequency offset Notes Performance Characteristics* - Functional 1 2 Holdover accuracy Holdover stability 3 4 Capture range Reference Out of Range Threshold (including hysteresis) -130 -64 -83 -40 -52 +130 +64 +83 +40 +52 ppm ppm 6 ppm Lock Time 7 14 Hz Filter 1.5 s 8 29 Hz Filter 1 s Output Phase Continuity (MTIE) 11 12 13 Reference switching Switching from Normal mode to Automatic Holdover mode Switching from Automatic Holdover mode to Normal mode 13 0 13 ns ns ns * Supply voltage and operating temperature are as per Recommended Operating Conditions. 25 Zarlink Semiconductor Inc. ZL30108 Data Sheet Performance Characteristics*: Measured Output Jitter - GR-253-CORE and T1.105.03 conformance Telcordia GR-253-CORE and ANSI T1.105.03 Jitter Generation Requirements Jitter Measurement Filter Limit in UI (1 UI = 6.4 ns) Signal OC-3 Interface 1 2 3 C19o Equivalent limit in time domain ZL30108 Maximum Jitter Generation Units 65 kHz to 1.3 MHz 12 kHz to1.3 MHz (Category II) 500 Hz to 1.3 MHz 0.15 UIpp 0.1 UIpp 0.01 UIrms 1.5 UIpp 0.96 0.64 64 9.65 0.22 0.22 24 0.22 nspp nspp psrms nspp * Supply voltage and operating temperature are as per Recommended Operating Conditions Performance Characteristics*: Measured Output Jitter - G.813 conformance (Option 1 and Option 2 ITU-T G.813 Jitter Generation Requirements Jitter Measurement Filter Limit in UI (1 UI = 6.4 ns) Signal Equivalent limit in time domain ZL30108 Maximum Jitter Generation Units STM-1 Option 1 Interface 1 2 3 C19o C19o 65 kHz to 1.3 MHz 500 Hz to 1.3 MHz 12 kHz to1.3 MHz 0.1 UIpp 0.5 UIpp 0.1 UIpp 0.64 3.22 0.64 0.22 0.22 0.22 nspp nspp nspp STM-1 Option 2 Interface * Supply voltage and operating temperature are as per Recommended Operating Conditions Performance Characteristics* - Unfiltered Intrinsic Jitter Signal 1 2 3 C19o (19.44 MHz) F8ko (8 kHz) F2ko (2 kHz) Max. [nspp] 0.5 0.5 0.5 Notes * Supply voltage and operating temperature are as per Recommended Operating Conditions. 26 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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